High Speed Inter-chip Signaling in CMOS Area Exam

Moore’s Law is a commonly accepted empirical relation that predicts the operating speed of an integrated circuits will double every 18 months. However, as the operating speed and functionality increases, the need to move data onto and off of the processor is increasing at a comparable rate, which is quantified using another empirical relation known as Rent’s Rule. Unfortunately, Rent’s rule states that the communication bandwidth is increasing at a slower rate (Figure 1-1), leading to a widening gap between the available and the required bandwidth, an issue that must be addressed in future systems in order to maintain a balanced system. In addition to maintaining balance, certain applications such as high speed fibre-optic SONET interfaces require extremely high speed interchip communications. State-of-the-art SONET systems are operating at channel rates of 10 Gb/s, and the next wave of systems will be operating with 40Gb/s of bandwidth per channel. As such, future systems need to be able to handle these extremely high speeds in a costefficient manner.